The present invention generally relates to the field of failure analysis and yield engineering, and more specifically relates to photoemission data collection.
Photoemission analysis is the technique of analyzing the photons emitted from an integrated circuit under various operating conditions. Most CMOS circuits consume very little power in a static state, hence emitting few photons. Depending on the type and size of a defect, a defective part may emit a large quantity of photons (light) which is detectable with specialized analysis equipment. Most photoemission occurs at the junction level of the device, in wavelengths in the infrared range. As silicon is transparent to infrared light, and due to the increasing number and density of metallization interconnect layers, one of the more effective methods of photoemission analysis involves imaging the die and analyzing the photoemission from the die under test from the back side of the wafer.
Current photoemission analysis techniques focus analysis on a single die/package or sub-circuit of an integrated circuit. The dataflow is illustrated in FIG. 1, and provides that an illuminated image of a die is acquired, power is applied to the Device Under Test (DUT), a photoemission image is acquired, and then the images are overlaid and aligned. This may be repeated for several die on the wafer, or on several packaged parts. Current photoemission techniques allow for the location and isolation of a photoemission site to within several microns accuracy. However, analysis on a die-by-die basis is a time-consuming process that limits the effectiveness of photoemission analysis as a yield management tool.